FIG. 1 is a schematic view of a conventional bias current circuit comprising: a first current path formed by connecting a PMOS transistor P1 and a NMOS transistor N1; a second current path formed by connecting a PMOS transistor P2, an NMOS transistor N2 and a resistor R1; and an output path formed of a PMOS transistor P3. The PMOS transistors P1, P2, P3 are connected to form a symmetric structure in which all their sources are connected to a supply voltage VCC and all their gates are connected to a node NET2. A bias current I1 is output from a drain of the PMOS transistor P3.
A drain of the PMOS transistor P1, a drain and a gate of the NMOS transistor N1 and a gate of the NMOS transistor N2 are all connected to a node NET1. A drain of the NMOS transistor N2 is connected to the node NET2.
A source of the NMOS transistor N1 is grounded, and the resistor R1 is connected between a source of the NMOS transistor N2 and the ground.
The bias current circuit of FIG. 1 can well operate when the supply voltage VCC is high. However, with the increasing popularity of handheld devices, more and more low-voltage and low-power applications are emerging, which pose a challenge because they require the existing bias current circuits in various analog circuits to be also able to well operate at lower supply voltages (e.g., the supply voltage VCC in FIG. 1). As known from FIG. 1, the operation of the circuit requires a voltage drop from the supply voltage VCC to the node NET2 that is higher than a threshold voltage of the PMOS transistor P1, as well as a voltage at the node NET1 that is higher than a threshold voltage of the NMOS transistor N1. Therefore, a decrease in the supply voltage VCC means lower voltages at the nodes NET1 and NET2, which may create a possibility of the voltage drop from the supply voltage VCC to the node NET2 and the voltage at the node NET1 approaching or even dropping below the threshold voltages of the corresponding PMOS transistor and the corresponding NMOS transistor, respectively. When this happens, the performance of the circuit will be impaired.